Cadence & NVIDIA Revolutionize AI Chip Power Analysis
In a significant advancement for the semiconductor industry, Cadence and NVIDIA have unveiled a collaborative breakthrough in pre-silicon power analysis, promising to revolutionize the design of energy-efficient AI and machine learning (ML) chips. Leveraging the sophisticated capabilities of the Cadence Palladium Z3 Enterprise Emulation Platform, coupled with the new Cadence Dynamic Power Analysis (DPA) App, the companies have achieved what was previously considered an insurmountable challenge: hardware-accelerated dynamic power analysis of billion-gate AI designs, spanning billions of operational cycles within mere hours, all while maintaining an impressive accuracy of up to 97 percent. This milestone is set to empower semiconductor and systems developers to create more energy-efficient systems and accelerate their products’ journey to market.
The escalating complexity and computational demands of contemporary semiconductors and systems have long posed a formidable hurdle for designers. Accurately predicting power consumption under realistic operating conditions has been elusive, as conventional power analysis tools typically struggle to scale beyond a few hundred thousand cycles without demanding impractical timelines. Through their close partnership, Cadence and NVIDIA have effectively overcome these limitations, employing innovations in hardware-assisted power acceleration and parallel processing. This allows for unprecedented precision across billions of cycles, even in the early stages of design.
Dhiraj Goswami, corporate vice president and general manager at Cadence, emphasized the deep-rooted collaboration underpinning this achievement. “Cadence and NVIDIA are building on our long history of introducing transformative technologies developed through deep collaboration,” Goswami stated. He highlighted the dramatic improvement in processing speed, noting that the project “redefined boundaries, processing billions of cycles in as few as two to three hours. This empowers customers to confidently meet aggressive performance and power targets and accelerate their time to silicon.”
Narendra Konda, vice president of Hardware Engineering at NVIDIA, echoed this sentiment, underscoring the critical need for advanced tools in the rapidly evolving landscape of AI. “As the era of agentic AI and next-generation AI infrastructure rapidly evolves, engineers need sophisticated tools to design more energy-efficient solutions,” Konda explained. He added that the synergy of NVIDIA’s expertise in accelerated computing with Cadence’s leadership in Electronic Design Automation (EDA) is “advancing hardware-accelerated power profiling to enable more precise efficiency in accelerated computing platforms.”
The Palladium Z3 Platform utilizes the DPA App to deliver accurate estimates of power consumption under real-world workloads. This crucial capability allows designers to verify functionality, power usage, and performance before the “tapeout” phase—the point at which the design is finalized for manufacturing—when optimizations can still be readily implemented. This early power modeling is particularly beneficial for AI, ML, and GPU-accelerated applications, as it not only enhances energy efficiency but also helps avoid costly delays stemming from over- or under-designed semiconductors. By integrating Palladium DPA into Cadence’s comprehensive analysis and implementation solution, designers can now address power estimation, reduction, and signoff throughout the entire design process, ultimately leading to the most efficient silicon and system designs possible.